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Technology Now

Introducing Mitsubishi Electric Power Device Technologies and Product Trends

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2: Development of the 6th-generation IGBT Chip
2-1: Power loss and power chip performance according to "Figure of Merit"

Common issues for power modules are "low power loss" and "miniaturization." Resolving these issues is a major prerequisite for continually higher functionality and the evolution of high performance in future generations. To achieve this, a superior power chip must be developed.

First, when examining the relationship between the power chip embedded in the power module and system power loss, replacing the bipolar transistors used in the 1980s with the 1st-generation chip resulted in a power loss reduction of approximately 30%. Following this, power loss continued to decline approximately 40% between the 1st and 3rd-generation chips, and the current 5th-generation chip loses only one-third to one-fourth of the power lost when the 1st-generation chip was used. These reductions in power loss have contributed immensely to low power consumption in practical applications, especially for the realization of amazingly low power consumption by inverter-equipped home electric appliances such as room air-conditioners.

Reduction of the Operating Loss in Power Devices

Next, I will introduce "Figure of Merit (FOM)," which is used to measure power chip performance. FOM is obtained by dividing the maximum electrical current density of the power chip by the "ON voltage and switching loss" of the product. The ON voltage represents the loss during conductance and TURN OFF loss is a characteristic value which indicates switching loss. Visible current density is added to conductive performance and FOM is made up of three characteristic values. The larger the FOM value, the better the performance.

IGBT FOM Improvement

FOM shows that performance improved approximately fourfold between the 1st and 3rd-generation chips. And if the performance of the 1st-generation chip is compared with that of the current 5th-generation chip, it has improved approximately tenfold. As we proceed with the development of the 6th-generation device, our aim is to achieve not only even lower power loss, but also an improvement in performance indicators of approximately 30% as compared to the 5th-generation chip.

2-2: Achieving low power loss through advanced structural technologies

The path from the collector to the emitter can be expressed as being divided into several elements of resistance. Resistance in the initial flat-surfaced IGBTs was caused by the junction field-effect transistor (JFET). To resolve this, a trench structure design was introduced for the 4th-generation chip, thereby eliminating the JFET resistance and making it possible to reduce conductance loss. For the 5th-generation chip, aiming to reduce loss further, a carrier collection layer was added to reduce bulk resistance. For the 6th-generation chip, we're pursuing further reduction in loss by altering the structure.

Change in IGBT Chip Structure

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