||2-3: Developing the 6th-generation power chip utilizing original breakthrough technologies
Mitsubishi Electric developed and introduced a superior power loss reducing structure called the Carrier-stored Trench Gate Bipolar Transistor (CSTBT™) for the 5th-generation IGBT chip. The 6th-generation IGBT chip is also being developed using the CSTBT™ structure.
Development of the 6th-generation chip is based on two core technologies: 1) "optimization of the impurity concentration profile," which is a structural technology for improving short-circuit resistance, and 2) "wafer microfabrication," which reduces ON voltage and widens the electrical current path.
As the number of transistor cells integrated into an IGBT chip determines how easily the electrical current flows, a major point in development is how many cells can be produced in the chip by reducing the trench interval. According to simulation results, reducing the trench interval from the current 4µm pitch to 2.5µm will reduce ON resistance, which is the conductance loss indicator, by approximately 20 - 30%.
||2-4: Concentration profile optimized to reduce threshold voltage variance
Using this technology, ON resistance is reduced, but there is a side effect of also reducing the safety operation area (SOA). Mitsubishi Electric has developed a "concentration profile optimization" technology that eliminates this side effect.
Gate threshold voltage is an indicator for determining the short-circuit resistance and SOA. A lower threshold voltage allows more electrical current but reduces the short-circuit resistance. Conversely, if the threshold voltage is high, short-circuit resistance is strong but electrical current is limited. In short, there is a trade-off relationship between electrical current capacity and short-circuit resistance, with threshold voltage serving as the parameter.
As mentioned above, the concentration profile optimization technology we have developed alleviates this trade-off relationship. When it comes to the structure of CSTBTs™, variations in manufacturing processes tend to easily influence characteristics such as threshold voltage. However, high-energy ion implantation technology is utilized to optimize the concentration profile of the 6th-generation chip, making it structurally more resistant to the effects of manufacturing process variations. By reducing the threshold voltage variance, more leeway is gained for designing the SOA, and the microfabrication process realizes a reduction in power loss. These two factors ensure a larger SOA.
• By reducing variance, a duration of 10µs is guaranteed with the same short-circuit load, L.
• For rated loss, switching loss is reduced by approximately 30% compared to the 5th-generation chip.
• In addition to improved performance, package size has been reduced approximately 30% compared to the previous NF Series.
• In an overall comparison with the 5th-generation chip, the ON voltage is reduced, with the variance halved from the previous ±1V to ±0.5V. Standard capacity is maintained and short-circuit resistance and SOA are secured, greatly improving the overall trade-off.